Sending audio and video data in real time requires the data rate at the transmitter and receiver to match in order to avoid impairing the reproduction quality as a result of underflows or overflows in buffer-stores for data (buffers). The receiver accordingly also needs to receive clock information which defines the exact data rate at all times. This clock information may come from the transmitter itself or else from an external clock reference, and in the latter case the transmitter also needs to be synchronized to this external clock reference.
In both cases, clock information needs to be distributed, however. In this context, the transmission is frequently not ideal, i.e. the clock is overlaid with jitter during distribution. For this reason, clock recovery is frequently used, the task of which is to suppress or reduce this jitter by means of filtering (and possibly also to multiply the clock frequency).
Clock recovery with jitter suppression is normally implemented by a phase trimming circuit PLL (phase-locked loop). The clock generator used for the PLL is frequently voltage controlled oscillators VCO. However, such VCOs have, as analog circuits, the drawback that they can be integrated on an application-specific integrated circuit ASIC only in complex fashion.
Digitally controlled oscillators DCO are far superior to an analog VCO not only in respect of their integratability in an ASIC but also in respect of their power and area requirements. Most DCOs are based on a DLL (Delay-Locked Loop) or on a ring oscillator. Although ring oscillators may be used for jitter suppression (jitter filtering), the low frequency resolution and the high susceptibility to natural jitter limit the range of application of ring oscillators. Although conventional DLL-based implementations of DCOs can multiply the frequency of the input signal, they provide no jitter filtering, since there is no genuine frequency synthesis involved.
A PLL with a DLL-based solution for a DCO has already been described in U.S. Pat. No. 2002/0008557. The DCO is clocked by a stable oscillator. In addition, the DCO comprises an adder which generates a desired output frequency. An input word is repeatedly added to a start value for the adder, so that the adder fills or overflows cyclically. Once the adder has filled or overflowed, a rising edge of the output signal is generated upon the next rising edge of the input clock (clock from the stable oscillator). If generation of the rising edge of the output signal produces a “remnant term” on the adder (that is to say if the input word added to the counter reading of the adder was larger than the remaining capacity of the adder), this remnant term (which is that part of the input word which exceeds the capacity of the adder) is written to a register and represents the timing error in the output signal. The remnant term is used to actuate a multistage delay circuit (coarse delay, fine delay). The delay circuit has a plurality of delay stages (coarse delay stage, fine delay stage), each delay stage being provided with individual discrete taps downstream of each delay element. In this case the remnant term controls which of the taps in the delay stage is respectively tapped off so that the output signal (which, of course, has a timing error which is represented by the remnant term) can be delayed such that the timing error in the output signal is compensated for when the correspondingly delayed output signal then has the correct phase again.
To select the respectively suitable tap, the delay stage contains a multiplexer (selector) whose inputs are connected to the individual taps downstream of the respective delay elements (specifically a respective input on the multiplexer is connected to a tap downstream of a delay element), so that the remnant term can actuate the multiplexer such that the corresponding tap is selected for which the output signal is delayed such that the timing error is compensated for.
This is done by virtue of a coarse delay stage taking the coarse delay elements it contains as a basis for first of all coarsely delaying the output signal. The coarse delay stage delays the output signal as closely as possible to the delay which is required in order to compensate for the timing error, as is possible on the basis of the delay by the individual coarse delay elements (at most just as far as the required delay; if this is not exactly possible on the basis of the delay by the individual coarse delay elements, then as far as that coarse delay which is just below the delay which is required for the compensation). The signal delayed by the coarse delay stage is then delayed further in at least one fine delay stage (or else in a plurality of fine delay stages) until the delay which is necessary in order to compensate for the timing error is reached (or as close to this as is actually possible on the basis of the delay by the individual fine delay elements). The fine delay stage is designed such that passing through all of the fine delay elements (maximum delay by the fine delay stage) brings about a delay which corresponds to exactly one coarse delay element.
The difference between the maximum and minimum delays by the entire delay circuit (coarse delay stage and fine delay stages) is exactly one period of the input clock (clock from the stable oscillator).
As already mentioned, the inputs of the multiplexer need to be connected to the many individual taps on a delay stage of this type, which causes significant difficulties for the implementation of such a delay stage in an integrated circuit (e.g. on silicon), because each tap downstream of a delay element needs to be connected to the input of the multiplexer by a connection of equal length (or in better terms: of equal shortness) so that no relevant propagation time differences arise on the path from the taps downstream of the individual delay elements to the inputs of the multiplexer (otherwise the accuracy of the delay would be impaired no less than considerably, if the operability were not actually seriously called into question).
In the case of the coarse delay stage described in U.S. Pat. No. 2002/0008557, these alone are 64 taps which need to be connected to the inputs of the multiplexer. However, beyond the 64 taps which are used, the individual delay stages normally also contain a significantly larger number of delay elements which are not always all used, however, but whose taps still need to be connected to the inputs of the multiplexer, because, depending on the application, it is, of course, not known beforehand how many delay elements are actually needed for a particular application. Hence, taking into account the stipulation that no relevant propagation time differences must arise, the difficulties in implementing a delay stage of this type in silicon become immediately clear upon consideration of the propagation time for the signals between respective taps and the associated inputs of the multiplexer.